Coursera - Computer Architecture

Coursera - Computer Architecture metadata, size 5301.05 MB, 121 files, category video, indexed at 2026-07-29.

大小:5.2 GB 格式:mp4 分类:视频 文件数量:121 个 发掘时间:2026-07-29 13:40:36 最后活跃:2026-07-29 13:40:36

资源标识

Infohashe833f8dbb2e48396f29818f8fdec19091d86a1a4 总大小5.2 GB 格式mp4 分类视频 文件数121 发掘时间(北京时间)2026-07-29 13:40:36 最后活跃(北京时间)2026-07-29 13:40:36

下载标识

完整磁力链接 magnet:?xt=urn:btih:e833f8dbb2e48396f29818f8fdec19091d86a1a4&dn=Coursera%20-%20Computer%20Architecture
迅雷地址 thunder://QUFtYWduZXQ6P3h0PXVybjpidGloOmU4MzNmOGRiYjJlNDgzOTZmMjk4MThmOGZkZWMxOTA5MWQ4NmExYTQmZG49Q291cnNlcmElMjAtJTIwQ29tcHV0ZXIlMjBBcmNoaXRlY3R1cmVaWg==
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文件列表

文件名格式大小
PS1_Solutions_Small.pdfpdf1.7 MB
PS1A.pdfpdf798.1 KB
PS1.pdfpdf126.1 KB
PS5_Solutions.pdfpdf867.7 KB
PS5A.pdfpdf551.5 KB
PS5.pdfpdf175.0 KB
PS2_Solutions_Small.pdfpdf788.2 KB
PS2.pdfpdf137.0 KB
PS4.pdfpdf163.2 KB
PS4A.pdfpdf250.1 KB
PS4_Solutions_Small.pdfpdf358.1 KB
PS3_Solutions.pdfpdf130.7 KB
PS3.pdfpdf174.4 KB
Computer Architecture 4.1 L4S2 Cache Performance (1711).mp4mp431.3 MB
Computer Architecture 4.0 L4S1 Classifying Caches (2807).mp4mp4159.7 MB
Computer Architecture 4.2 L4S3 Superscalar 1 (642).mp4mp413.5 MB
Computer Architecture 4.4 L4S5 Fetch Logic and Alignment (1101).mp4mp419.1 MB
Computer Architecture 4.3 L4S4 Basic Two-way In-order Superscalar (456).mp4mp49.5 MB
Computer Architecture 17.1 L17S2 Locks and Semaphores (1001).mp4mp418.9 MB
Computer Architecture 17.0 L17S1 Sequential Consistency Review (348).mp4mp48.5 MB
Computer Architecture 17.4 L17S5 Dekker's Algorithm (1413).mp4mp428.6 MB
Computer Architecture 17.3 L17S4 Memory Fences (1111).mp4mp422.7 MB
Computer Architecture 17.2 L17S3 Atomic Operations (2711).mp4mp451.3 MB
Computer Architecture 1.5 L1S6 ISA Characteristics (2547).mp4mp458.0 MB
Computer Architecture 1.4 L1S5 Machine Models (1602).mp4mp432.8 MB
Computer Architecture 1.2 L1S3 Course Content (910).mp4mp425.8 MB
Computer Architecture 1.0 L1S1 Course Overview (434).mp4mp418.2 MB
Computer Architecture 1.3 L1S4 Architecture and Microarchitecture (2337).mp4mp452.8 MB
Computer Architecture 1.6 L1S7 Recap (0117).mp4mp41.9 MB
Computer Architecture 1.1 L1S2 Motivation (1640).mp4mp495.0 MB
Computer Architecture 11.2 L11S3 Write Buffers (952).mp4mp421.5 MB
Computer Architecture 11.4 L11S5 Victim Caches (604).mp4mp458.5 MB
Computer Architecture 11.0 L11S1 Basic Cache Optimizations (1608).mp4mp434.5 MB
Computer Architecture 11.3 L11S4 Multilevel Caches (1737).mp4mp452.8 MB
Computer Architecture 11.5 L11S6 Prefetching (1234).mp4mp4148.9 MB
Computer Architecture 11.1 L11S2 Cache Pipelining (1416).mp4mp428.4 MB
Computer Architecture 18.1 L18S2 Bus Implementation (1211).mp4mp469.3 MB
Computer Architecture 18.4 L18S5 Cache Coherence Protocols (4900).mp4mp4249.9 MB
Computer Architecture 18.3 L18S4 Bus-Based Multiprocessors (516).mp4mp430.1 MB
Computer Architecture 18.2 L18S3 Cache Coherence (1704).mp4mp497.6 MB
Computer Architecture 18.0 L18S1 Locking Review (204).mp4mp411.9 MB
Computer Architecture 13.3 L13S4 Translation and Protection (1437).mp4mp433.6 MB
Computer Architecture 13.0 L13S1 Memory Management Introduction (1304).mp4mp432.1 MB
Computer Architecture 13.2 L13S3 Page Based Memory Systems (2704).mp4mp4154.8 MB
Computer Architecture 13.4 L13S5 TLB Processing (1200).mp4mp426.0 MB
Computer Architecture 13.1 L13S2 Base and Bound Registers (1144).mp4mp426.0 MB
Computer Architecture 7.3 L7S4 Register Renaming with Values in IQ and ROB (1214).mp4mp467.6 MB
Computer Architecture 7.2 L7S3 Register Renaming with Pointers to IQ and ROB (2454).mp4mp4141.8 MB
Computer Architecture 7.1 L7S2 Register Renaming Introduction (1108).mp4mp463.3 MB
Computer Architecture 7.0 L7S1 Speculation and Branch (1437).mp4mp429.1 MB

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